1. Field of the Invention
The present invention relates to integrated circuits utilizable for recovering incoming digital data and, in particular, to a receiver squelch circuit that utilizes sample data techniques for pulse-width filtering.
2. Discussion of the Prior Art
The IEEE 802.3 standard for 10BASE-T Ethernet networks specifies a receiver filtering requirement for incoming data signals. According to the standard, the receiver must reject all signals that are not within the 2-15 MHz frequency range as well as all sine waves of single cycle duration. In addition, the receiver must be capable of recognizing the 250 ns Ethernet active-to-idle transition pulse as an End-of-Packet (EOP) symbol, thereby terminating reception.
Conventional bandpass filters are not suitable for 10BASE-T receiver applications because they do not reject single cycle data nor are they sensitive to the EOP pulse. In addition, bandpass filters are not amplitude-sensitive.
Therefore, it is necessary that a new receiver circuit be provided to meet 802.3 10BASE-T Ethernet requirements.
U.S. Pat. No. 5,285,481, referenced above, discloses a receiver circuit that utilizes analog pulse width timer/integrators to filter data signals having a frequency less than a preselected maximum and greater than a preselected minimum. The circuit also rejects a single sine wave cycle. If an input pulse greater than a preselected maximum pulse width, e.g. the 10BASE-T EOP pulse width, is encountered during data reception, then reception activity is terminated.
While the receiver squelch circuit disclosed in the U.S. Pat. No. 5,285,481 provides a simple, yet elegant solution for meeting the 10BASE-T receiver filter requirement, it is a full analog solution, which, although utilizable in CMOS/BiCMOS receivers, would be much simpler to incorporate in such receivers if implemented in CMOS.
It would, therefore, be highly desireable to have available a CMOS implementation that meets the IEEE 802.3 10BASE-T Ethernet receiver filter standard.